Design solutions for Atmel SPLD/CPLD



Mandeno Granville Electronics can offer design services for Atmel SPLD/CPLD.

We have done over 200 SPLD/CPLD designs using Atmel family PLDs, and have a wide range of IP and resources available for customers.

We are able to hand-map and create high resource usage, often lowering the cost of deployment.

Preferred tool chain is Atmel WinCUPL, as that allows the best low-level access to the device resource, and it gives a stable and fast design environment, well suited to the types of design projects that map onto Atmel PLDs.

We can also provide Stand alone PLD Programmers, that complement the ISP solutions :

These programmers support Vector testing ( and Vector Edit / Vector Save ) of SPLD/CPLD up to 44 pin CPLDs, and programming support up to 100 pins, and on those devices, 36 io pins can be vector tested.
By placing the Silicon INSIDE the design loop, you verify all stages,and avoid the 'is this a SW BUG, or my problem ?', uncertainty.
Volume Production, Teaching and Design Lab solutions are available.


Universal Programmers

We have a family of universal Programmers, from low cost models, to high speed, high performance production and test programmers. The advanced models use FPGA's for high speed, fully configurable pin drivers,and full vector tests.

  • TopMAX-2 Universal FAST DIP48/PLCC44 Programmer and 44 Pin Vector Tester

  • TopMAX Universal FAST DIP48/PLCC44 Programmer and 44 Pin Vector Tester

  • ChipMAX-2 Universal DIP48/ Programmer and 48 Pin Vector Tester

  • ChipMAX Universal DIP40 Programmer and 24 Pin Vector Tester

Features available are

  • Programming of std EPROM/FLASH/EEPROM

  • Programming of PLD,CPLD, and FPGA 17xxx (F)PROMS

  • FULL Vector Test, AFTER program, to fully verify design

  • Parallel port operation of programmers

  • FAST startup, and BATCH commands supported, for production

  • Self Test, and Chip Test features

  • Do not loose JTAG pins, and can recover devices with JTAG off fuse set

  • SW designed for Speed, and ease of use

Why Vector Testing?

Unlike EPROMS, with PLD's, it is not enough to simply PGM & VERIFY. This has only tested the PROM array inside the PLD, not the PLD logic nor PLD pins. Vector testing applies test stimulus waveforms ( vectors ), generated by the CUPL simulator, to the PLD pins, and reports the results. Advantages of test vectors are many:

  • Allows rigorous design loop process

  • Version control, and revisions, are much safer

  • Gives REAL SILICON confirm of the simulated results, avoids 'gotchas'

  • HW can be run BEFORE the PCB design is complete, & Pinlock confirmed

  • Provides a good way to verify an already SECURED device

  • Much easier to trouble shoot, than a new PCB layout

  • Greatly speeds production, as only PROVEN parts are used

  • FAST - typically a few seconds to run



Contact: Jim Granville
E-Mail [remove reverse spam]: PLDinfo_2006@DesignTools.maps.co.nz
FAX: +64 9 6301 720