Mandeno Granville Electronics can offer design services for Atmel SPLD/CPLD.
We have done over 200 SPLD/CPLD designs using Atmel family PLDs, and have a wide range of IP and resources available for customers.
We are able to hand-map and create high resource usage, often lowering the cost of deployment.
Preferred tool chain is Atmel WinCUPL, as that allows the best low-level access to the device resource, and it gives a stable and fast design environment, well suited to the types of design projects that map onto Atmel PLDs.
We can also provide Stand alone PLD Programmers, that complement the ISP solutions :
These programmers support Vector testing ( and Vector Edit /
Vector Save ) of SPLD/CPLD up to 44 pin CPLDs, and programming
support up to 100 pins, and on those devices, 36 io pins can be
We have a family of universal Programmers, from low cost models, to high speed, high performance production and test programmers. The advanced models use FPGA's for high speed, fully configurable pin drivers,and full vector tests.
Features available are
Why Vector Testing?
Unlike EPROMS, with PLD's, it is not enough to simply PGM & VERIFY. This has only tested the PROM array inside the PLD, not the PLD logic nor PLD pins. Vector testing applies test stimulus waveforms ( vectors ), generated by the CUPL simulator, to the PLD pins, and reports the results. Advantages of test vectors are many: